Software and hardware

LangGraph and LangChain agents

This project: a LangGraph graph with Send fan-out, interrupt() for human approval, SQLite checkpointing and structured output whose schemas leave no field for a number, and a fleet of those graphs, orchestrated by code around a shared LangGraph Store. Also a LangGraph coding agent with sub-agents, MCP tools and a local Ollama provider.

Personal projects:HW_Design_Space_AgentRaschka_Coding_Agent_LangGraph

Python simulators and models

Deterministic, tested models that other code is checked against: the bit-exact CORDIC golden model and cost model here, an agent-loop simulator, and a SimPy discrete-event simulator of disaggregated LLM serving.

Personal projects:Agent_Loop_SimDisaggregated_Inference_Sim

TypeScript and Next.js

This site and a family of animated explainer sites, each driven by a TypeScript port that reproduces its Python reference exactly, rendered statically, with Web Workers for the heavy models.

Personal projects:Agent Harnesses ExplainedAgent Protocols ExplainedAgent Context Explained

Testing and CI

Parity tests between languages with no tolerance, frame tests on every animation, end-to-end tests at desktop and phone widths in light and dark mode, accessibility scans and Lighthouse budgets in CI; in the agent's CI, generated RTL checked against the golden model in two simulators, formal proofs, gate-level simulation and a synthesis smoke test.

Personal projects:this site's CIthe agent's CI

MCP

Hands-on Model Context Protocol playgrounds: tools, resources and prompts servers behind a gateway and an SSE bridge, each with a web client.

Personal projects:MCP_Gateway_PlaygroundMCP_Supergateway_Playground

FPGA and RTL

SystemVerilog and VHDL, Xilinx certified, UltraScale+. Public examples: the synthesisable CORDIC modules this project starts from, and this project's generator of verified SystemVerilog for four CORDIC architectures (synthesised with Yosys, nextpnr-xilinx and Vivado 2025.2 for the FPGA, and with Yosys and OpenSTA on the open sky130 PDK); a parameterised AXI4 crossbar, a MESI cache controller, and an AHB-to-MII Ethernet MAC in VHDL with its testbench and verification plans.

Personal projects:CORDICHW_Design_Space_AgentAXI4_CrossbarCache_Controller_MESIVHDL_example_code

SoC and RISC-V

A RISC-V SoC integrating a 5-stage RV32IMC CPU, an AXI4 crossbar, MMUs, a MESI cache, DMA, an IOMMU and a PLIC, each verified on its own first.

Personal projects:RISCV_SoC

Power: multiphase DC-DC and PDN

Multiphase DC-DC conversion and power-delivery-network design. Public example: DC-DC converter control (PWM, PFM, hysteretic and constant on-time, with load-transient comparisons).

Personal projects:DCDC_Control_Techniques

Signal and power integrity, thermal

Seventeen interactive decks on signal integrity and high-speed digital design in which every number is computed by a model and checked against published work.

Personal projects:Signal_Integrity

PCB: HDI, DDR, PCIe and MIPI

High-density boards with DDR, PCIe and MIPI interfaces: schematic and layout practice, design for manufacture and board bring-up.

DSP (MSc)

Signal processing, the subject of an MSc. Public example: a collection of browser-based DSP, synthesis and analysis projects.

Personal projects:DSP_and_Music