/roadmap

Roadmap

Each milestone takes the same spec one rung further down the fidelity ladder. Status comes from the roadmap in the repository's README at 80415c6; as each milestone merges, this site re-vendors the repository, flips the badges and animates the new levels from real runs.

1. M1

   live (M1)

   The agent itself: spec intake with a human in the loop, LLM-steered exploration over tested fast models, the exhaustive ground truth and the eval against NSGA-II and random search with real models.

   • L0 Spec intake
   • L1 Analytical exploration

   README: “L0 spec intake (NL/YAML → validated Spec, human confirmation) · L1 analytical exploration (LLM-chosen families and ranges, Optuna multi-objective search over fast cost models, Pareto front) · baseline eval” (done)

   HW_Design_Space_Agent #1 (merged)this site, part A (merged)this site, part B (merged)

2. M2

   live (M2)

   From estimates to measurements, and the whole trade-off curve: one generator of SystemVerilog for every family, verified against the golden model in Verilator and Icarus and with SymbiYosys proofs; open-source synthesis and place-and-route (Yosys + nextpnr-xilinx) and gate-level simulation of the netlist; back-annotation that refits the cost model per tool and flags a winner change; front-mapping levers for the agent, and a five-seed eval. Then a follow-up pull request: Vivado 2025.2 on 14 generated designs and the vivado-2025.2 refit (no spec's winner changed; the default cost model stays M1's).

   • L3 RTL simulation
   • L4 Synthesis
   • GL Gate-level simulation of the netlist
   • L5 Back-annotation

   README: “L3 SystemVerilog generator for every family, verified against the golden model (Verilator + Icarus, exhaustive for W ≤ 16), SymbiYosys proofs (W = 8) · L4 open-source synthesis + place-and-route (Yosys + nextpnr-xilinx), gate-level simulation of the netlist · L5 measured-points schema, per-tool refit of the cost model, back-annotation node that flags a winner change · whole-curve agent levers · 5-seed eval” (done)

   README, M2 follow-ups: “Vivado 2025.2 on 14 generated designs, refit vivado-2025.2” (done)

   README: “measured power (Vivado report_power, 14 designs) · high_precision m=8 and m=6 synthesised at a 20 ns constraint · refit vivado-2025.2-m4 · per-family-class path factor decided (rejected by a rule fixed beforehand)” (done: M4 local runs)

   HW_Design_Space_Agent #3: M2 (merged)HW_Design_Space_Agent #4: L5 with Vivado 2025.2 (merged)this site's pull requests

3. M3

   live (M3)

   The design in its system: a cycle-accurate model of every family's interface, checked against the generated RTL cycle for cycle, and SimPy models of three systems (a DDS feeding a mixer, a control loop, a bursty request stream); system-level specs, screened at L1 by optimistic bounds and re-selected at L2 on simulated numbers; an L5 loop that re-explores under the refit when a measurement changes the winner; a gated fix for M2's front-mapping blind spot; and a campaign agent on LangChain Deep Agents with cross-run memory, measured in an A/B against the structured graph. The A/B found no gain at a higher cost, so the campaign agent stays experimental, off by default.

   • SYS System-level simulation (SimPy)
   • L2 Cycle-level simulation

   README: “L2 cycle-accurate interface model per family (validated against the RTL cycle for cycle) + SimPy system models (DDS + mixer, control loop, bursty stream) · system-level constraints in specs, L1 bounds, L2 shortlist and re-selection · L5 loop: re-explore under the refit when a measured winner changes · map_front blind-spot fix (gated lever) · M2 replay proof · campaign agent on Deep Agents with cross-run memory · A/B and memory on/off eval” (done: see the A/B for what the campaign agent did and did not achieve)

   README: “live L4 inside campaigns · any campaign-agent rework (only if the M4 fleet design needs it)” (planned)

   HW_Design_Space_Agent #5: M3 (merged)this site's pull requests

4. M4

   live (M4)

   A second target and a fleet: the same generated RTL synthesised on the open sky130 PDK (Yosys + OpenSTA, post-synthesis only, no place and route), an ASIC cost model fitted to 57 measured designs and checked on 9 held-out ones, three ASIC specs with exhaustive ground truth and FPGA twins; a fleet of structured graphs orchestrated by code around a shared LangGraph Store, in a paired A/B against the single graph; L2 → L1 feedback that corrects the system bound when the simulation rejects every candidate; the exports for a local Vivado run (run after M4, below); and the final write-up. The fleet mapped the front worse and, with Qwen, selected better; the ASIC model's winner misses its deadline when measured. Both are stated plainly on the results page.

   • ASIC Synthesis on sky130 (standard cells)

   README: “ASIC target: Yosys + OpenSTA on sky130_fd_sc_hd (57-point sweep, 9 held-out designs), fitted AsicCostModel with leave-one-out residuals, target in specs, three ASIC specs with exhaustive ground truth, ASIC back-annotation · fleet of structured graphs, code-orchestrated, shared LangGraph Store, A/B vs a single graph · L2 → L1 feedback · FPGA replay proof extended to M3 · Vivado exports for the local run · [docs/WRITEUP.md](docs/WRITEUP.md)” (done: see the A/B for what the fleet did and did not achieve)

   README: “place and route on the ASIC target (OpenROAD) · an ASIC measure-and-re-explore loop (synthesise the selected designs, re-select under measured numbers), then a decision on an unrolled_k chain term, disclosed, with the held-out points kept held out · an LLM coordinator for the fleet · more functions and a richer family registry” (planned)

   HW_Design_Space_Agent #6: M4 (merged)HW_Design_Space_Agent #7: the local Vivado runs (merged)this site's pull requests

How each milestone was planned, verified and decided is in the project record. See also how it works and the results, and the final write-up.